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IISWC
2006
IEEE
15 years 3 months ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...
PPAM
2007
Springer
15 years 3 months ago
Using HLA and Grid for Distributed Multiscale Simulations
Combining simulations of different scale in one application is non-trivial issue. This paper proposes solution that supports complex time interactions that can appear between elem...
Katarzyna Rycerz, Marian Bubak, Peter M. A. Sloot
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 2 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
73
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CASES
2006
ACM
15 years 1 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...
ECAI
2008
Springer
14 years 11 months ago
Learning in Planning with Temporally Extended Goals and Uncontrollable Events
Recent contributions to advancing planning from the classical model to more realistic problems include using temporal logic such as LTL to express desired properties of a solution ...
André A. Ciré, Adi Botea