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DAC
2008
ACM
15 years 11 months ago
Parameterized timing analysis with general delay models and arbitrary variation sources
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
Khaled R. Heloue, Farid N. Najm
DAC
2007
ACM
15 years 11 months ago
Automatic Verification of External Interrupt Behaviors for Microprocessor Design
Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This pap...
Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang
DAC
1999
ACM
15 years 11 months ago
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton,...
DAC
2000
ACM
15 years 11 months ago
Multiple Si layer ICs: motivation, performance analysis, and design implications
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...
DAC
2002
ACM
15 years 11 months ago
ILP-based engineering change
We have developed a generic integer linear programming(ILP)based engineering change(EC) methodology. The EC methodology has three components: enabling, fast, and preserving. Enabl...
Farinaz Koushanfar, Jennifer L. Wong, Jessica Feng...
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