Sciweavers

27354 search results - page 5406 / 5471
» Distributed And Parallel Computing
Sort
View
CASES
2008
ACM
14 years 11 months ago
Cache-aware cross-profiling for java processors
Performance evaluation of embedded software is essential in an early development phase so as to ensure that the software will run on the embedded device's limited computing r...
Walter Binder, Alex Villazón, Martin Schoeb...
CCS
2008
ACM
14 years 11 months ago
Code injection attacks on harvard-architecture devices
Harvard architecture CPU design is common in the embedded world. Examples of Harvard-based architecture devices are the Mica family of wireless sensors. Mica motes have limited me...
Aurélien Francillon, Claude Castelluccia
CCS
2008
ACM
14 years 11 months ago
Reducing protocol analysis with XOR to the XOR-free case in the horn theory based approach
In the Horn theory based approach for cryptographic protocol analysis, cryptographic protocols and (Dolev-Yao) intruders are modeled by Horn theories and security analysis boils d...
Ralf Küsters, Tomasz Truderung
CCS
2008
ACM
14 years 11 months ago
The risk-utility tradeoff for IP address truncation
Network operators are reluctant to share traffic data due to security and privacy concerns. Consequently, there is a lack of publicly available traces for validating and generaliz...
Martin Burkhart, Daniela Brauckhoff, Martin May, E...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 11 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
« Prev « First page 5406 / 5471 Last » Next »