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HPCA
2009
IEEE
16 years 7 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
IPPS
2006
IEEE
16 years 15 days ago
Exploiting processing locality through paging configurations in multitasked reconfigurable systems
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
T. Taher, Tarek A. El-Ghazawi
VTC
2008
IEEE
119views Communications» more  VTC 2008»
16 years 26 days ago
On the Design of a Quality-Of-Service Driven Routing Protocol for Wireless Cooperative Networks
—In this paper, a quality-of-service driven routing protocol is proposed for wireless cooperative networks. The key contribution of the proposed protocol is to bring the performa...
Zhengguo Sheng, Zhiguo Ding, Kin K. Leung
GLOBECOM
2007
IEEE
16 years 25 days ago
A Link-Layer Channel Model for IEEE 802.11 Ad Hoc Networks
— This paper presents a novel stochastic link-layer channel model for IEEE 802.11 ad hoc networks. The model characterizes the variations of the channel service process in a non-...
Atef Abdrabou, Weihua Zhuang
IPPS
2006
IEEE
16 years 15 days ago
Node-disjoint paths in hierarchical hypercube networks
The hierarchical hypercube network is suitable for massively parallel systems. An appealing property of this network is the low number of connections per processor, which can faci...
Ruei-Yu Wu, J. G. Chang, Gen-Huey Chen