3346 search results - page 340 / 670 » Distributed Caching Platforms |
121
Voted
HIPS
1998
IEEE
15 years 8 months ago
1998
IEEE
Distributed shared objects are a well known approach to achieve independenceof the memory model for parallel programming. The illusion of shared (global) objects is a conabstracti...
117
Voted
HPCA
2008
IEEE
16 years 4 months ago
2008
IEEE
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
183
Voted
HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
120
Voted
HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
135
Voted
HPCA
2003
IEEE
16 years 4 months ago
2003
IEEE
This paper identifies node affinity as an important property for scalable general-purpose locks. Nonuniform communication architectures (NUCAs), for example CCNUMAs built from a f...