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    ISVLSI
    2007
    IEEE
    204views VLSI» more  ISVLSI 2007»
    Designing Memory Subsystems Resilient to Process Variations
    15 years 9 months ago
    Designing Memory Subsystems Resilient to Process Variations
    Download  www.ecs.umass.edu
    As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
    Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
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    79
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    ICS
    2009
    Tsinghua U.
    124views Distributed And Parallel Com...» more  ICS 2009»
    Access map pattern matching for data cache prefetch
    15 years 9 months ago
    Access map pattern matching for data cache prefetch
    Download  scfdb.tokyo.jst.go.jp
    Yasuo Ishii, Mary Inaba, Kei Hiraki
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    72
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    EUROPAR
    2004
    Springer
    78views Distributed And Parallel Com...» more  EUROPAR 2004»
    Contents Management in First-Level Multibanked Data Caches
    15 years 8 months ago
    Contents Management in First-Level Multibanked Data Caches
    Download  webdiis.unizar.es
    Enrique F. Torres, Pablo Ibáñez, V&i...
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    96
    Voted
    ICS
    2004
    Tsinghua U.
    120views Distributed And Parallel Com...» more  ICS 2004»
    Detailed cache coherence characterization for OpenMP benchmarks
    15 years 8 months ago
    Detailed cache coherence characterization for OpenMP benchmarks
    Download  moss.csc.ncsu.edu
    Jaydeep Marathe, Anita Nagarajan, Frank Mueller
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    88
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    EUROPAR
    2003
    Springer
    101views Distributed And Parallel Com...» more  EUROPAR 2003»
    Counteracting Bank Misprediction in Sliced First-Level Caches
    15 years 8 months ago
    Counteracting Bank Misprediction in Sliced First-Level Caches
    Download  webdiis.unizar.es
    Enrique F. Torres, Pablo Ibáñez, V&i...
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