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IPPS
2003
IEEE
15 years 3 months ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
IPPS
1998
IEEE
15 years 2 months ago
Efficient Runtime Thread Management for the Nano-Threads Programming Model
Abstract. The nano-threads programming model was proposed to effectively integrate multiprogramming on shared-memory multiprocessors, with the exploitation of fine-grain parallelis...
Dimitrios S. Nikolopoulos, Eleftherios D. Polychro...
99
Voted
ICPADS
2010
IEEE
14 years 8 months ago
M-cube: A Duty Cycle Based Multi-channel MAC Protocol with Multiple Channel Reservation for WSNs
In this paper, a duty cycle based multi-channel MAC protocol with multiple channel reservation, called M-cube, is proposed to tackle the triple hidden terminal problems. M-cube can...
Jinbao Li, Desheng Zhang, Longjiang Guo, Shouling ...
HPCA
2008
IEEE
15 years 10 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
87
Voted
ISHPC
2000
Springer
15 years 1 months ago
Limits of Task-Based Parallelism in Irregular Applications
Traditional parallel compilers do not effectively parallelize irregular applications because they contain little looplevel parallelism due to ambiguous memory references. We explo...
Barbara Kreaseck, Dean M. Tullsen, Brad Calder