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161
Voted
DFT
2009
IEEE
175views VLSI» more  DFT 2009»
16 years 2 months ago
Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories
Hybrid CMOS/non-CMOS memories, in short hybrid memories, have been lauded as future ultra-capacity data memories. Nonetheless, such memories are going to suffer from high degree o...
Nor Zaidi Haron, Said Hamdioui
ICVS
2009
Springer
16 years 2 months ago
White-Box Evaluation of Computer Vision Algorithms through Explicit Decision-Making
Traditionally computer vision and pattern recognition algorithms are evaluated by measuring differences between final interpretations and ground truth. These black-box evaluations ...
Richard Zanibbi, Dorothea Blostein, James R. Cordy
191
Voted
CHI
2010
ACM
16 years 1 months ago
Speech dasher: fast writing using speech and gaze
Speech Dasher allows writing using a combination of speech and a zooming interface. Users first speak what they want to write and then they navigate through the space of recognit...
Keith Vertanen, David J. C. MacKay
149
Voted
WCNC
2008
IEEE
16 years 1 months ago
Genetic Algorithm Aided Design of Near-Capacity Irregular Variable Length Codes
— In this paper we demonstrate that our ability to match the EXtrinsic Information Transfer (EXIT) function of an Irregular Variable Length Code (IrVLC) to that of a seriallyconc...
Robert G. Maunder, Lajos Hanzo
198
Voted
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
16 years 1 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra