Formalized study of self-assembly has led to the definition of the tile assembly model, Previously I presented ways to compute arithmetic functions, such as addition and multiplic...
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
Srinivas Chellappa, Franz Franchetti, Markus P&uum...
The widespread use of Grid technology and distributed compute power, with all its inherent benefits, will only be established if the use of that technology can be guaranteed effic...
This paper explores low-power reliable microarchitectures for addition. Power, speed, and reliability (both defect- and fault-tolerance) are important metrics of system design, sp...
Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray R...
— Achieving high performance for out-of-core applications typically involves explicit management of the movement of data between the disk and the physical memory. We are developi...
Sriram Krishnamoorthy, Juan Piernas, Vinod Tippara...