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131
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IPPS
2003
IEEE
15 years 9 months ago
2003
IEEE
This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. This paper has three main goals. The first one is to present the tren...
154
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ICDCS
2002
IEEE
15 years 9 months ago
2002
IEEE
We present a generic module, called Fast Collect. Fast Collect is an implementation of Single-Writer Multi-Reader (SWMR) Shared-Memory in an asynchronous system in which a process...
164
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JSSPP
2001
Springer
15 years 9 months ago
2001
Springer
The Maui scheduler has received wide acceptance in the HPC community as a highly configurable and effective batch scheduler. It is currently in use on hundreds of SP, O2K, and Li...
134
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SPDP
1991
IEEE
15 years 8 months ago
1991
IEEE
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
143
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JPDC
2000
15 years 4 months ago
2000
A new class of interconnection networks, the hypernetworks, has been proposed recently. Hypernetworks are characterized by hypergraphs. Compared with point-to-point networks, they...