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ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
15 years 8 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
ESCIENCE
2006
IEEE
15 years 8 months ago
CIMA Based Remote Instrument and Data Access: An Extension into the Australian e-Science Environment
The Common Instrument Middleware Architecture (CIMA) is being used as a core component of a portal based remote instrument access system being developed as an Australian e-Science...
Ian M. Atkinson, Douglas du Boulay, Clinton Chee, ...
146
Voted
ICS
2007
Tsinghua U.
15 years 8 months ago
Proactive fault tolerance for HPC with Xen virtualization
Large-scale parallel computing is relying increasingly on clusters with thousands of processors. At such large counts of compute nodes, faults are becoming common place. Current t...
Arun Babu Nagarajan, Frank Mueller, Christian Enge...
IEEEPACT
2007
IEEE
15 years 8 months ago
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...
Marek Olszewski, Jeremy Cutler, J. Gregory Steffan
EUROPAR
2009
Springer
15 years 6 months ago
Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures
Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Perfor...
Cédric Augonnet, Samuel Thibault, Raymond N...