122 search results - page 14 / 25 » Distributed Reorder Buffer Schemes for Low Power |
95
Voted
IEEEPACT
2009
IEEE
15 years 4 months ago
2009
IEEE
Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not...
CF
2005
ACM
14 years 11 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
HPCA
2004
IEEE
15 years 10 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
SASN
2004
ACM
15 years 3 months ago
2004
ACM
Sensor networks are composed of a large number of low power sensor devices. For secure communication among sensors, secret keys must be established between them. Recently, several...
CORR
2007
Springer
14 years 9 months ago
2007
Springer
— We consider a dense fading multi-user network with multiple active multi-antenna source-destination pair terminals communicating simultaneously through a large common set of K ...