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HPCA
2009
IEEE
16 years 1 months ago
A low-radix and low-diameter 3D interconnection network design
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
Bo Zhao, Jun Yang 0002, Xiuyi Zhou, Yi Xu, Youtao ...
SBCCI
2003
ACM
96views VLSI» more  SBCCI 2003»
15 years 5 months ago
SoCIN: A Parametric and Scalable Network-on-Chip
Networks-on-Chip (NoCs) interconnection architectures to be used in future billion-transistor Systems-on-Chip (SoCs) meet the major communication requirements of these systems, of...
Cesar Albenes Zeferino, Altamiro Amadeu Susin
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
15 years 13 days ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
IPPS
1999
IEEE
15 years 4 months ago
NetCache: A Network/Cache Hybrid for Multiprocessors
In this paper we propose the use of an optical network not only as the communication medium, but also as a system-wide cache for the shared data in a multiprocessor. More specifica...
Enrique V. Carrera, Ricardo Bianchini
114
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SIGCOMM
2005
ACM
15 years 6 months ago
ExOR: opportunistic multi-hop routing for wireless networks
This paper describes ExOR, an integrated routing and MAC protocol that increases the throughput of large unicast transfers in multi-hop wireless networks. ExOR chooses each hop of...
Sanjit Biswas, Robert Morris