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EUROPAR
2010
Springer
15 years 7 months ago
Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
Fenglong Song, Dongrui Fan, Zhiyong Liu, Junchao Z...
CORR
2010
Springer
148views Education» more  CORR 2010»
15 years 6 months ago
Data Sharing Options for Scientific Workflows on Amazon EC2
Efficient data management is a key component in achieving good performance for scientific workflows in distributed environments. Workflow applications typically communicate data be...
Gideon Juve, Ewa Deelman, Karan Vahi, Gaurang Meht...
167
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HPCA
2011
IEEE
14 years 10 months ago
Shared last-level TLBs for chip multiprocessors
Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as c...
Abhishek Bhattacharjee, Daniel Lustig, Margaret Ma...
HPCA
2012
IEEE
14 years 1 months ago
Balancing DRAM locality and parallelism in shared memory CMP systems
Modern memory systems rely on spatial locality to provide high bandwidth while minimizing memory device power and cost. The trend of increasing the number of cores that share memo...
Min Kyu Jeong, Doe Hyun Yoon, Dam Sunwoo, Mike Sul...
ICC
2007
IEEE
129views Communications» more  ICC 2007»
16 years 20 days ago
Time Sharing Policy in Wireless Networks for Variable Rate Transmission
— For most of wireless services with variable rate transmission, both average rate and rate oscillation are important performance metrics. One often needs to decide how much rate...
Xiaolu Zhang, Meixia Tao, Chun Sum Ng