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HPCA
2005
IEEE
16 years 4 months ago
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihi...
HPCA
2005
IEEE
16 years 4 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
HPCA
2004
IEEE
16 years 4 months ago
Out-of-Order Commit Processors
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
Adrián Cristal, Daniel Ortega, Josep Llosa,...
HPCA
2003
IEEE
16 years 4 months ago
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...
Russ Joseph, David Brooks, Margaret Martonosi
POPL
2005
ACM
16 years 4 months ago
Transition predicate abstraction and fair termination
on Predicate Abstraction and Fair Termination Andreas Podelski Andrey Rybalchenko Max-Planck-Institut f?ur Informatik Saarbr?ucken, Germany Predicate abstraction is the basis of m...
Andreas Podelski, Andrey Rybalchenko
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