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ICS
2007
Tsinghua U.
15 years 4 months ago
Performance driven data cache prefetching in a dynamic software optimization system
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
Jean Christophe Beyler, Philippe Clauss
ICS
2007
Tsinghua U.
15 years 4 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
IWMM
2007
Springer
146views Hardware» more  IWMM 2007»
15 years 4 months ago
Allocation-phase aware thread scheduling policies to improve garbage collection performance
Past studies have shown that objects are created and then die in phases. Thus, one way to sustain good garbage collection efficiency is to have a large enough heap to allow many ...
Feng Xian, Witawas Srisa-an, Hong Jiang
HICSS
2006
IEEE
163views Biometrics» more  HICSS 2006»
15 years 4 months ago
Learning Ranking vs. Modeling Relevance
The classical (ad hoc) document retrieval problem has been traditionally approached through ranking according to heuristically developed functions (such as tf.idf or bm25) or gene...
Dmitri Roussinov, Weiguo Fan
ICNP
2006
IEEE
15 years 4 months ago
Orthogonal Rendezvous Routing Protocol for Wireless Mesh Networks
— Routing in multi-hop wireless networks involves the indirection from a persistent name (or ID) to a locator. Concepts such as coordinate space embedding help reduce the number ...
Bow-Nan Cheng, Murat Yuksel, Shivkumar Kalyanarama...