Sciweavers

855 search results - page 97 / 171
» Distributed musical performances: Architecture and stream ma...
Sort
View
HOTI
2005
IEEE
15 years 3 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
GLVLSI
2010
IEEE
136views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Thermal-aware compilation for system-on-chip processing architectures
The development of compiler-based mechanisms to reduce the percentage of hotspots and optimize the thermal profile of large register files has become an important issue. Thermal...
Mohamed M. Sabry, José L. Ayala, David Atie...
SOSP
2009
ACM
15 years 6 months ago
The multikernel: a new OS architecture for scalable multicore systems
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
Andrew Baumann, Paul Barham, Pierre-Évarist...
SENSYS
2005
ACM
15 years 3 months ago
TSAR: a two tier sensor storage architecture using interval skip graphs
Archival storage of sensor data is necessary for applications that query, mine, and analyze such data for interesting features and trends. We argue that existing storage systems a...
Peter Desnoyers, Deepak Ganesan, Prashant J. Sheno...
ICAC
2007
IEEE
15 years 4 months ago
Towards Autonomic Fault Recovery in System-S
System-S is a stream processing infrastructure which enables program fragments to be distributed and connected to form complex applications. There may be potentially tens of thous...
Gabriela Jacques-Silva, Jim Challenger, Lou Degena...