139 search results - page 21 / 28 » Distributed sleep transistor network for power reduction |
101
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VLSID
2010
IEEE
15 years 1 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
88
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HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
JSA
2006
14 years 9 months ago
2006
Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable m...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...