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DAC
2006
ACM
16 years 5 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
DAC
2006
ACM
16 years 5 months ago
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis
We propose a scalable and efficient parameterized block-based statistical static timing analysis algorithm incorporating both Gaussian and non-Gaussian parameter distributions, ca...
Jaskirat Singh, Sachin S. Sapatnekar
COORDINATION
2009
Springer
16 years 5 months ago
Multicore Scheduling for Lightweight Communicating Processes
Process-oriented programming is a design methodology in which software applications are constructed from communicating concurrent processes. A process-oriented design is typically ...
Carl G. Ritson, Adam T. Sampson, Fred R. M. Barnes
HPCA
2009
IEEE
16 years 5 months ago
Elastic-buffer flow control for on-chip networks
This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel b...
George Michelogiannakis, James D. Balfour, William...
VLSID
2007
IEEE
85views VLSI» more  VLSID 2007»
16 years 5 months ago
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo s...
Elias Kougianos, Saraju P. Mohanty
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