Sciweavers

7379 search results - page 1146 / 1476
» Distributed vector architectures
Sort
View
HPCA
2006
IEEE
16 years 4 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
146
Voted
EDBT
2004
ACM
139views Database» more  EDBT 2004»
16 years 4 months ago
GRIDS, Databases, and Information Systems Engineering Research
GRID technology, emerging in the late nineties, has evolved from a metacomputing architecture towards a pervasive computation and information utility. However, the architectural de...
Keith G. Jeffery
PPOPP
2010
ACM
16 years 1 months ago
Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
Eddy Z. Zhang, Xipeng Shen, Yunlian Jiang
203
Voted
ICCD
2008
IEEE
420views Hardware» more  ICCD 2008»
16 years 1 months ago
Frequency and voltage planning for multi-core processors under thermal constraints
— Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance op...
Michael Kadin, Sherief Reda
142
Voted
ICDE
2009
IEEE
171views Database» more  ICDE 2009»
15 years 11 months ago
CoTS: A Scalable Framework for Parallelizing Frequency Counting over Data Streams
Applications involving analysis of data streams have gained significant popularity and importance. Frequency counting, frequent elements and top-k queries form a class of operato...
Sudipto Das, Shyam Antony, Divyakant Agrawal, Amr ...
« Prev « First page 1146 / 1476 Last » Next »