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ASAP
2006
IEEE
169views Hardware» more  ASAP 2006»
15 years 11 months ago
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
Hritam Dutta, Frank Hannig, Jürgen Teich, Ben...
ESCIENCE
2006
IEEE
15 years 11 months ago
Hybrid Particle Guide Selection Methods in Multi-Objective Particle Swarm Optimization
This paper presents quantitative comparison of the performance of different methods for selecting the guide particle for multi-objective particle swarm optimization (MOPSO). Two p...
David Ireland, Andrew Lewis, Sanaz Mostaghim, Junw...
KIVS
2011
Springer
14 years 7 months ago
Alister 2.0 - Programmable Logic Controllers in Railway Interlocking Systems for Regional Lines of the DB Netze AG
Railway interlockings are dominated by highly proprietary systems. We present the development project Alister 2.0 – an interlocking system based on industry-proven standard comp...
Reiner Saykowski, Elferik Schultz, Joachim Bleidie...
CCECE
2011
IEEE
14 years 5 months ago
Resistively and capacitively shunted Josephson junctions model for unconventional superconductors
—An array of resistively and capacitively shunted Josephson junctions with nonsinusoidal currentphase relation is considered for modelling the resistive transition in high-Tc sup...
Linda Ponta, Anna Carbone, Marco Gilli, Piero Mazz...
IBPRIA
2007
Springer
15 years 11 months ago
Topological Histogram Reduction Towards Colour Segmentation
Abstract. One main process in Computer Vision is image segmentation as a tool to other visual tasks. Although there are many approaches to grey scale image segmentation, nowadays m...
Eduard Vazquez, Ramon Baldrich, Javier Vazquez, Ma...