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ASPLOS
2009
ACM
16 years 2 months ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
WSDM
2010
ACM
166views Data Mining» more  WSDM 2010»
15 years 11 months ago
Ranking Mechanisms in Twitter-Like Forums
We study the problem of designing a mechanism to rank items in forums by making use of the user reviews such as thumb and star ratings. We compare mechanisms where forum users rat...
Anish Das Sarma, Atish Das Sarma, Sreenivas Gollap...
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
15 years 10 months ago
Obstacle-avoiding rectilinear Steiner tree construction
— In today’s VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important prob...
Liang Li, Evangeline F. Y. Young
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
15 years 10 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ICCAD
2005
IEEE
125views Hardware» more  ICCAD 2005»
15 years 10 months ago
Robust mixed-size placement under tight white-space constraints
A novel and very simple correct-by-construction top-down methodology for high-utilization mixed-size placement is presented. The PolarBear algorithm combines recursive cutsize-dri...
Jason Cong, Michail Romesis, Joseph R. Shinnerl