We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Z...
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zh...
We propose a scalable and efficient parameterized block-based statistical static timing analysis algorithm incorporating both Gaussian and non-Gaussian parameter distributions, ca...