Sciweavers

1912 search results - page 207 / 383
» Don't Compare Averages
Sort
View
DATE
2007
IEEE
96views Hardware» more  DATE 2007»
15 years 8 months ago
Self-heating-aware optimal wire sizing under Elmore delay model
Global interconnect temperature keeps rising in the current and future technologies due to self-heating and the adiabatic property of top metal layers. The thermal e ects impact a...
Min Ni, Seda Ogrenci Memik
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
15 years 8 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
DATE
2007
IEEE
155views Hardware» more  DATE 2007»
15 years 8 months ago
A novel technique to use scratch-pad memory for stack management
Extensive work has been done for optimal management of scratch-pad memory (SPM) all assuming that the SPM is assigned a fixed address space. The main target objects to be placed o...
Soyoung Park, Hae-woo Park, Soonhoi Ha
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
15 years 8 months ago
Improving utilization of reconfigurable resources using two dimensional compaction
Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the rec...
Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. ...
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
15 years 8 months ago
Double-via-driven standard cell library design
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Run...