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DATE
2007
IEEE
150views Hardware» more  DATE 2007»
15 years 8 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
DATE
2007
IEEE
154views Hardware» more  DATE 2007»
15 years 8 months ago
Soft error rate analysis for sequential circuits
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...
Natasa Miskov-Zivanov, Diana Marculescu
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
15 years 8 months ago
Fast memory footprint estimation based on maximal dependency vector calculation
In data dominated applications, loop transformations have a huge impact on the lifetime of array data and therefore on memory footprint. Since a locally optimal loop transformatio...
Qubo Hu, Arnout Vandecappelle, Per Gunnar Kjeldsbe...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 8 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
DFT
2007
IEEE
112views VLSI» more  DFT 2007»
15 years 8 months ago
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model
During semiconductor manufacturing, particles undesirably depose on the surface of the wafer causing “open” and “short” defects to interconnects. In this paper, a third ty...
Rani S. Ghaida, Payman Zarkesh-Ha