Parameter variation is detrimental to a processor’s frequency and leakage power. One proposed technique to mitigate it is Fine-Grain Body Biasing (FGBB), where different parts o...
Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Jose...
Abstract--The average throughput of three decode-andforward (DF) half-duplex (DFHD) and two DF full-duplex (DFFD) rateless coded relaying schemes are studied under a peak power con...
We propose a novel approach to shape-based image retrieval that builds upon a similarity criterion which is based on the average point set distance. Compared to traditional techni...
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pa...
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...