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ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
15 years 10 months ago
A New Statistical Optimization Algorithm for Gate Sizing
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
Murari Mani, Michael Orshansky
ICCD
2003
IEEE
115views Hardware» more  ICCD 2003»
15 years 10 months ago
Reducing Compilation Time Overhead in Compiled Simulators
Compiled simulation is a well known technique for improving the performance of instruction set simulators at the cost of compilation time. However the compilation time overhead ma...
Mehrdad Reshadi, Nikil D. Dutt
ICCAD
2007
IEEE
132views Hardware» more  ICCAD 2007»
15 years 10 months ago
Principle Hessian direction based parameter reduction with process variation
— As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessi...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
ICCAD
2006
IEEE
125views Hardware» more  ICCAD 2006»
15 years 10 months ago
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Ha...
ICCAD
2004
IEEE
121views Hardware» more  ICCAD 2004»
15 years 10 months ago
Factoring and eliminating common subexpressions in polynomial expressions
Polynomial expressions are used to compute a wide variety of mathematical functions commonly found in signal processing and graphics applications, which provide good opportunities...
Anup Hosangadi, Farzan Fallah, Ryan Kastner