55 search results - page 3 / 11 » Double-via-driven standard cell library design |
CASES
2009
ACM
15 years 4 months ago
2009
ACM
Efficient hardware architectures for the Luffa hash algorithm are proposed in this work. We explore different tradeoffs and propose several architectures, targeting both compac...
VLSID
2006
IEEE
15 years 3 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
Electrical Modeling for High Bandwidth IO Link Chirayu Amin, Chandramouli Kashyap ¬ Intel Corp., Hillsboro, OR Prateek Bhansali ¬ Univ. of Minnesota, Mi...
59
Voted
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
80
Voted
CHES
2006
Springer
15 years 1 months ago
2006
Springer
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...