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CHES
2005
Springer
100views Cryptology» more  CHES 2005»
15 years 5 months ago
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on imple...
Thomas Popp, Stefan Mangard
CTRSA
2005
Springer
108views Cryptology» more  CTRSA 2005»
15 years 5 months ago
A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box
This work proposes a compact implementation of the AES S-box using composite field arithmetic in GF(((22 ) 2 ) 2 ). It describes a systematic exploration of different choices for...
Nele Mentens, Lejla Batina, Bart Preneel, Ingrid V...
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
15 years 5 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte
ASAP
2004
IEEE
140views Hardware» more  ASAP 2004»
15 years 3 months ago
Decimal Floating-Point Division Using Newton-Raphson Iteration
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
Liang-Kai Wang, Michael J. Schulte
DAC
2002
ACM
16 years 20 days ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou