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ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
15 years 1 months ago
Processor-programmable memory BIST for bus-connected embedded memories
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
Ching-Hong Tsai, Cheng-Wen Wu
TRUST
2010
Springer
15 years 2 months ago
Robust Combiners for Software Hardening
All practical software hardening schemes, as well as practical encryption schemes, e.g., AES, were not proven to be secure. One technique to enhance security is robust combiners. A...
Amir Herzberg, Haya Shulman
IEEEPACT
2006
IEEE
15 years 3 months ago
A low-cost memory remapping scheme for address bus protection
The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to critical information leakage such as encryp...
Lan Gao, Jun Yang 0002, Marek Chrobak, Youtao Zhan...
FMOODS
2003
14 years 11 months ago
Managing the Evolution of .NET Programs
Abstract. The component-based model of code execution imposes some requirements on the software components themselves, and at the same time lays some constraints on the modern run-...
Susan Eisenbach, Vladimir Jurisic, Chris Sadler
RTA
2004
Springer
15 years 2 months ago
A Visual Environment for Developing Context-Sensitive Term Rewriting Systems
Over the past decade, researchers have found context-sensitive term-rewriting semantics to be powerful and expressive tools for modeling programming languages, particularly in esta...
Jacob Matthews, Robert Bruce Findler, Matthew Flat...