46 search results - page 9 / 10 » Drowsy Caches: Simple Techniques for Reducing Leakage Power |
GLVLSI
2002
IEEE
13 years 11 months ago
2002
IEEE
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active...
ICS
2003
Tsinghua U.
13 years 11 months ago
2003
Tsinghua U.
—The ever-increasing computational power of contemporary microprocessors reduces the execution time spent on arithmetic computations (i.e., the computations not involving slow me...
VEE
2006
ACM
14 years 11 days ago
2006
ACM
During recent years, microprocessor energy consumption has been surging and efforts to reduce power and energy have received a lot of attention. At the same time, virtual executio...
DATE
2007
IEEE
14 years 23 days ago
2007
IEEE
In deep submicron circuits, elevation in temperatures has brought new challenges in reliability, timing, performance, cooling costs and leakage power. Conventional thermal managem...
ISCA
2007
IEEE
14 years 21 days ago
2007
IEEE
From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within po...