132 search results - page 21 / 27 » Dynamic Adaptation of Parallelism Level in Data Transfer Sch... |
DSD
2002
IEEE
15 years 2 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
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DCOSS
2010
Springer
15 years 2 months ago
2010
Springer
Most sensor network applications are dominated by the acquisition of sensor values. Due to energy limitations and high energy costs of communication, in-network processing has been...
CGF
2008
14 years 9 months ago
2008
Algebraic Point Set Surfaces (APSS) define a smooth surface from a set of points using local moving least-squares (MLS) fitting of algebraic spheres. In this paper we first revisi...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...