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108
Voted
DATE
2006
IEEE
135views Hardware» more  DATE 2006»
15 years 8 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
111
Voted
IEEEARES
2010
IEEE
15 years 11 days ago
A New DRM Architecture with Strong Enforcement
—We propose a new DRM architecture that utilizes a two-step enforcement process to enable strong security even in the case of a compromised DRM viewer. This is achieved by using ...
Sascha Müller, Stefan Katzenbeisser
102
Voted
DAC
1999
ACM
15 years 6 months ago
An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications
Cordula Hansen, Francisco Nascimento, Wolfgang Ros...
92
Voted
DAC
1993
ACM
15 years 6 months ago
Resistance Extraction using a Routing Algorithm
Lorenz Ladage, Rainer Leupers