: A series of hypotheses is proposed, connecting neural structures and dynamics with the formal structures and processes of probabilistic logic. First, a hypothetical connection is...
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
Core operations (e.g. TDMA scheduler, synchronized sleep period, data aggregation) of many proposed protocols for different layer of sensor network necessitate clock synchronizatio...
Md. Mamun-Or-Rashid, Choong Seon Hong, Jinsung Cho
The last few years have seen a renewal of interest in the consideration of dynamic programming in compiler technology. This is due to the compactness of the representations, which...
Manuel Vilares Ferro, Miguel A. Alonso, David Cabr...
We present a new approach to partial-order reduction for model checking software. This approach is based on initially exploring an arbitrary interleaving of the various concurrent...