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JUCS
2007
102views more  JUCS 2007»
15 years 5 months ago
The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
Oscar Pérez, Yves Berviller, Camel Tanougas...
ISLPED
1995
ACM
131views Hardware» more  ISLPED 1995»
15 years 9 months ago
Guarded evaluation: pushing power management to logic synthesis/design
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
Vivek Tiwari, Sharad Malik, Pranav Ashar
TLCA
2007
Springer
15 years 12 months ago
A Substructural Type System for Delimited Continuations
We propose type systems that abstractly interpret small-step rather than big-step operational semantics. We treat an expression or evaluation context as a structure in a linear log...
Oleg Kiselyov, Chung-chieh Shan
TABLEAUX
2000
Springer
15 years 9 months ago
Benchmark Analysis with FaCT
FaCT (Fast Classification of Terminologies) is a Description Logic (DL) classifier that can also be used for modal logic satisfiability testing. The FaCT system includes two reason...
Ian Horrocks
POPL
2011
ACM
14 years 8 months ago
Dynamic inference of static types for ruby
There have been several efforts to bring static type inference to object-oriented dynamic languages such as Ruby, Python, and Perl. In our experience, however, such type inference...
Jong-hoon (David) An, Avik Chaudhuri, Jeffrey S. F...