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MICRO
2007
IEEE
141views Hardware» more  MICRO 2007»
15 years 5 months ago
Composable Lightweight Processors
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
Changkyu Kim, Simha Sethumadhavan, M. S. Govindan,...
BSN
2006
IEEE
111views Sensor Networks» more  BSN 2006»
15 years 5 months ago
A Compact, Wireless, Wearable Sensor Network for Interactive Dance Ensembles
We describe the design of a compact, wireless sensor module meant to capture expressive gestures in real-time when worn at the hands and feet of a dancer. Each sensor node include...
Ryan Aylward, S. Daniel Lovell, Joseph A. Paradiso
MICRO
2006
IEEE
102views Hardware» more  MICRO 2006»
15 years 5 months ago
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multi...
Sangyeun Cho, Lei Jin
83
Voted
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
15 years 5 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
HPCA
2005
IEEE
15 years 5 months ago
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important, and this necessitates the development of ...
Krishnan Sundaresan, Nihar R. Mahapatra