50 search results - page 5 / 10 » Dynamic FPGA routing for just-in-time FPGA compilation |
99
Voted
ERSA
2007
15 years 1 months ago
2007
”C to Gates” compilers for FPGAs have been a topic of investigation for nearly two decades. Some of these endeavors have reached a point of viability. Impulse C, for example, ...
98
Voted
ISLPED
2003
ACM
15 years 4 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
88
Voted
FCCM
2006
IEEE
15 years 5 months ago
2006
IEEE
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
117
Voted
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
118
Voted
MAM
2007
14 years 11 months ago
2007
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...