167 search results - page 9 / 34 » Dynamic Functional Unit Assignment for Low Power |
110
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ASPDAC
2011
ACM
14 years 1 months ago
2011
ACM
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
There has been an increased interest in design of that it can give better performance, if a modified noise broadband (data rate >IMSPS) delta sigma ADCs with over- transfer func...
IBMRD
2006
14 years 9 months ago
2006
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
101
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ICA3PP
2010
Springer
15 years 2 months ago
2010
Springer
Abstract. Finite volume numerical methods have been widely studied, implemented and parallelized on multiprocessor systems or on clusters. Modern graphics processing units (GPU) pr...
KES
2005
Springer
15 years 2 months ago
2005
Springer
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...