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ERSA
2009
131views Hardware» more  ERSA 2009»
15 years 1 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
WSC
1998
15 years 4 months ago
Experiments in Load Migration and Dynamic Load Balancing in SPEEDES
It is well known that the performance of a parallel discreteevent simulation (PDES) depends on the allocation of the workload to processors. In particular, poor performance may be...
Linda F. Wilson, Wei Shen
INFOCOM
2008
IEEE
15 years 9 months ago
Self-Organizing Dynamic Fractional Frequency Reuse in OFDMA Systems
—We describe an algorithm for sub-carrier and power allocation that achieves out-of-cell interference avoidance through dynamic fractional frequency reuse (FFR) in downlink of ce...
Alexander L. Stolyar, Harish Viswanathan
EUROMICRO
1999
IEEE
15 years 7 months ago
Delft-Java Dynamic Translation
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
C. John Glossner, Stamatis Vassiliadis
DAC
2012
ACM
13 years 5 months ago
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
Diverse IP cores are integrated on a modern system-on-chip and share resources. Off-chip memory bandwidth is often the scarcest resource and requires careful allocation. Two of t...
Min Kyu Jeong, Mattan Erez, Chander Sudanthi, Nige...