Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Wireless mesh networks recently emerge as a flexible, low-cost and multipurpose networking platform with wired infrastructure connected to the Internet. A critical issue in mesh ...
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
In this article, we describe the results from our survey in the ITdepartment of a large Oil and Gas company in Norway (Statoil ASA), in order to characterize developers’ views o...
Odd Petter N. Slyngstad, Anita Gupta, Reidar Conra...
We propose a hydraulic user interface consisting of an array of spray jets and the appropriate fluid sensing and fluid flow control systems for each jet, so that the device fun...