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IEEEPACT
2006
IEEE
15 years 11 months ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
IPPS
2006
IEEE
15 years 11 months ago
Battery-aware router scheduling in wireless mesh networks
Wireless mesh networks recently emerge as a flexible, low-cost and multipurpose networking platform with wired infrastructure connected to the Internet. A critical issue in mesh ...
Chi Ma, Zhenghao Zhang, Yuanyuan Yang
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
15 years 11 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
ISESE
2006
IEEE
15 years 11 months ago
An empirical study of developers views on software reuse in statoil ASA
In this article, we describe the results from our survey in the ITdepartment of a large Oil and Gas company in Norway (Statoil ASA), in order to characterize developers’ views o...
Odd Petter N. Slyngstad, Anita Gupta, Reidar Conra...
ISM
2006
IEEE
81views Multimedia» more  ISM 2006»
15 years 11 months ago
Water Jets as Pixels: Water Fountains as Both Sensors and Displays
We propose a hydraulic user interface consisting of an array of spray jets and the appropriate fluid sensing and fluid flow control systems for each jet, so that the device fun...
Steve Mann, Michael Georgas, Ryan E. Janzen
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