175 search results - page 19 / 35 » Dynamic Load Distribution in the Borealis Stream Processor |
120
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ICS
2007
Tsinghua U.
15 years 5 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
EUROPAR
1995
Springer
15 years 3 months ago
1995
Springer
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance ga...
84
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IEEEPACT
2006
IEEE
15 years 5 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
81
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IPPS
2006
IEEE
15 years 5 months ago
2006
IEEE
There are many application classes where the users are flexible with respect to the output quality. At the same time, there are other constraints, such as the need for real-time ...
102
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PACT
2009
Springer
15 years 4 months ago
2009
Springer
In this paper, we design and implement an efficient technique for parallel evidence propagation on state-of-the-art multicore processor systems. Evidence propagation is a major ste...