8232 search results - page 1533 / 1647 » Dynamic Logic Programming |
156
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FPGA
2010
ACM
16 years 1 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
136
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MDM
2009
Springer
15 years 11 months ago
2009
Springer
—This paper assumes a set of n mobile sensors that move in the Euclidean plane as a swarm. Our objectives are to explore a given geographic region by detecting spatio-temporal ev...
157
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SACMAT
2009
ACM
15 years 11 months ago
2009
ACM
In both the commercial and defense sectors a compelling need is emerging for highly dynamic, yet risk optimized, sharing of information across traditional organizational boundarie...
137
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CODES
2007
IEEE
15 years 11 months ago
2007
IEEE
In this paper we present an approach to the scheduling and voltage scaling of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded sys...
138
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ICC
2007
IEEE
15 years 11 months ago
2007
IEEE
—A H-WRR (Hierarchical Weighted Round-Robin) EPON (Ethernet Passive Optical Network) DBA (Dynamic Bandwidth Allocation) algorithm is devised and investigated. WRR table entries h...