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» Dynamic Memory Allocation for Large Query Execution
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MICRO
2005
IEEE
114views Hardware» more  MICRO 2005»
15 years 5 months ago
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
Sam S. Stone, Kevin M. Woley, Matthew I. Frank
DCOSS
2006
Springer
15 years 3 months ago
Y-Threads: Supporting Concurrency in Wireless Sensor Networks
Abstract. Resource constrained systems often are programmed using an eventbased model. Many applications do not lend themselves well to an event-based approach, but preemptive mult...
Christopher Nitta, Raju Pandey, Yann Ramin
LFCS
2009
Springer
15 years 6 months ago
Completeness Results for Memory Logics
Memory logics are a family of modal logics in which standard relational structures are augmented with data structures and additional operations to modify and query these structure...
Carlos Areces, Santiago Figueira, Sergio Mera
CGO
2006
IEEE
15 years 5 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
86
Voted
ICCD
2003
IEEE
129views Hardware» more  ICCD 2003»
15 years 8 months ago
Reducing dTLB Energy Through Dynamic Resizing
Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant ...
Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubr...