473 search results - page 44 / 95 » Dynamic Memory Design for Low Data-Retention Power |
143
Voted
ISLPED
2003
ACM
15 years 9 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
139
Voted
CF
2005
ACM
15 years 5 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
157
Voted
ISCA
2011
IEEE
14 years 7 months ago
2011
IEEE
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
122
Voted
CF
2005
ACM
15 years 5 months ago
2005
ACM
The common approach to reduce cache conflicts is to increase the associativity. From a dynamic power perspective this associativity comes at a high cost. In this paper we present...
136
Voted
CODES
2007
IEEE
15 years 7 months ago
2007
IEEE
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...