473 search results - page 46 / 95 » Dynamic Memory Design for Low Data-Retention Power |
116
Voted
DAC
2006
ACM
16 years 4 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
136
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HPCA
2005
IEEE
15 years 9 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
123
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CDES
2006
15 years 5 months ago
2006
Fast Fourier Transform (FFT) is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication applications. many of t...
140
Voted
ISCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
142
Voted
OSDI
1994
ACM
15 years 5 months ago
1994
ACM
Mobile computers such as notebooks, subnotebooks, and palmtops require low weight, low power consumption, and good interactive performance. These requirements impose many challeng...