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» Dynamic Memory Design for Low Data-Retention Power
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113
Voted
DAC
2007
ACM
16 years 4 months ago
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
Behnam Amelifard, Massoud Pedram
161
Voted
INFOCOM
2005
IEEE
15 years 9 months ago
IPStash: a set-associative memory approach for efficient IP-lookup
—IP-Lookup is a challenging problem because of the increasing routing table sizes, increased traffic, and higher speed links. These characteristics lead to the prevalence of hard...
Stefanos Kaxiras, Georgios Keramidas
ICCAD
2009
IEEE
109views Hardware» more  ICCAD 2009»
15 years 1 months ago
Energy reduction for STT-RAM using early write termination
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
Ping Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang
125
Voted
ICS
2005
Tsinghua U.
15 years 9 months ago
A performance-conserving approach for reducing peak power consumption in server systems
The combination of increasing component power consumption, a desire for denser systems, and the required performance growth in the face of technology-scaling issues are posing eno...
Wesley M. Felter, Karthick Rajamani, Tom W. Keller...
115
Voted
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
15 years 8 months ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi