473 search results - page 7 / 95 » Dynamic Memory Design for Low Data-Retention Power |
IOLTS
2008
IEEE
15 years 3 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
IWSOC
2005
IEEE
15 years 3 months ago
2005
IEEE
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
PATMOS
2005
Springer
15 years 3 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
ICCD
2008
IEEE
15 years 4 months ago
2008
IEEE
— SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability...
CODES
2001
IEEE
15 years 1 months ago
2001
IEEE
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...