473 search results - page 9 / 95 » Dynamic Memory Design for Low Data-Retention Power |
107
Voted
ICCAD
1995
IEEE
15 years 3 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
90
Voted
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
ICCD
2002
IEEE
15 years 8 months ago
2002
IEEE
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
87
Voted
DAC
2001
ACM
16 years 18 days ago
2001
ACM
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be d...
88
Voted
DAC
2000
ACM
16 years 18 days ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...