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IPPS
2000
IEEE
13 years 10 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi
FPL
2006
Springer
95views Hardware» more  FPL 2006»
13 years 10 months ago
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor
This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target application...
Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, K...
VLSI
2007
Springer
14 years 15 days ago
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor
Replacing functional units of an extensible processor with reconfigurable functional units enhances performance and flexibility of processors to execute custom instructions. That ...
Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Za...
CGO
2006
IEEE
14 years 14 days ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
MICRO
2010
IEEE
119views Hardware» more  MICRO 2010»
13 years 1 months ago
Task Superscalar: An Out-of-Order Task Pipeline
We present Task Superscalar, an abstraction of instruction-level out-of-order pipeline that operates at the tasklevel. Like ILP pipelines, which uncover parallelism in a sequential...
Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex...