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» Dynamic Simultaneous Multithreaded Architecture
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IEEEPACT
2007
IEEE
15 years 8 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
ICCCN
2007
IEEE
15 years 8 months ago
Lagniappe: Multi-* Programming Made Simple
—The emergence of multi-processor, multi-threaded architectures (referred to as multi- architectures) facilitates the design of high-throughput request processing systems (e.g., ...
Taylor L. Riché, R. Greg Lavender, Harrick ...
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POPL
2010
ACM
15 years 9 days ago
S-Net for multi-memory multicores
S-NET is a declarative coordination language and component technology aimed at modern multi-core/many-core architectures and systems-on-chip. It builds on the concept of stream pr...
Clemens Grelck, Jukka Julku, Frank Penczek
MASCOTS
2007
15 years 3 months ago
Adaptive Sampling for Efficient MPSoC Architecture Simulation
—Modern micro-architecture simulators are many orders of magnitude slower than the hardware they simulate. The use of multiprocessor architectures for supporting future mobile an...
Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar
HPCA
2007
IEEE
16 years 2 months ago
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
Stijn Eyerman, Lieven Eeckhout